A full functional Monolithic Active Pixel Sensor prototype for the CEPC vertex detector

The proposed Circular Electron-Positron Collider (CEPC) presents new challenges for pixel detectors in terms of cell size and functionality. A high data rate digital design and readout architecture of a Monolithic Active Pixel Sensor (MAPS) prototype for the CEPC vertex detector is presented. The MAPS prototype, together with the column drain based readout architecture, benefiting from the ALPIDE (ALice PIxel DEtector) and FE-I3 approaches, has been implemented to achieve high spatial resolution, fast readout, and low power consumption. The simulation results indicate the readout logic works properly with input data rates of 120MHz; while both analog front-end and in-pixel readout logic meet the 25ns bunch spacing constraint.