A 2.5GHz LTE Doherty Power Amplifier in SOI-CMOS Technology

The need for RF Front-Ends Module (FEM) with reduced size and cost is driving research towards highly integrated Power Amplifiers (PA) with challenging linearity and efficiency requirements. To overcome efficiency challenges, the Doherty PA (DPA) architecture represents an attractive solution because of its high back-off efficiency and relatively simple structure. This paper presents a state-of-the art SOI CMOS DP A design implemented in a 0.13um SOI CMOS industrial process. At 2.5GHz, the 2-stage SOI CMOS DPA achieves a measured peak PAE of 57% at 32.7dBm output power under 3.4V voltage supply. At IdB compression point, output power and PAE are 32.4dBm and 56% respectively. With a 10MHz LTE uplink signal, a linear output power of 29.4dBm is measured with a PAE of 48.8% at an ACLR level of -33dBc without using DPD.