FPGA-Accelerated Hash Join Operation for Relational Databases

Equi-join operations are fundamental in database management. Hash join algorithms are often used to reduce the computational complexity of join operations; however, their performance is influenced by imperfect data distributions caused by hash collisions. To resolve these collisions, this brief designs a hardware-accelerated hash join architecture. This architecture aims to break the trade-off between complex hash functions, which is computationally expensive, and hash join performance. First, two hash functions are employed to distribute data as evenly as possible, and then multiple entries of the collision list are provided; finally, a small number of the static random-access memory (SRAM) of the field-programmable gate arrays (FPGAs) are used to conduct the join operation in parallel. The proposed method yields high-throughput and is resource-efficient, as it does not require reprocessing of data; further, it improves hash table utilization. The results of implementing this architecture on a Xilinx Zynq FPGA platform indicate an accelerated throughput that is a minimum of 4.2× that of previous hardware-accelerated hash join methods.