Optimized method for protection of SiC JFET based converters against failure of auxiliary power supply

This paper presents a simple method to protect normally-on SiC JFET during loss of auxiliary power supply. The normally-on SiC JFET has attracted attention of many researchers due to their benefits such as high blocking voltage, low specific on-resistance, higher operating temperature, low output capacitance, reduced conduction and switching loss. However, the normally-on behavior of the SiC JFET introduces challenges to protect them during supply power-on transition, loss of auxiliary supply, power supply glitches, etc. Such fault events can easily cause the shoot-through and catastrophic damage of the power electronic system if proper protection circuit is not designed. The solution proposed in this paper uses relatively less components and it is compared against state-of-the-art solutions to show its simplicity and benefits. The concept is validated with scaled down experimental prototype as well as some analysis is presented based on simulations. The results show that the proposed method works correct by keeping the SiC JFETs off for long enough time to de-energize the DC bus during loss of auxiliary power supply.