Power Reduction of Half Adder and Half Subtractor Using Different Partial Adiabatic Logic Styles

With the increasing growth of VLSI technologies the number of gates per chip is constantly increasing, as a result power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issue in low power circuits in VLSI design. Adiabatic logic is a promising technique used in low power VLSI circuits to achieve high level of performance with limiting power consumption. In Adiabatic logic, power consumption /dissipation occurring at the time of switching event is avoidable as the power supply retrieve the charge from node capacitance without heat generation which is contradict to conventional CMOS logic style and also power saving more than 50% is achievable in case of partial adiabatic circuits when compared to conventional CMOS circuits but with increase in circuit complexity. The simulation is carried out for half adder and half subtractor using 180nm CMOS technology in Cadence Virtuoso environment. From the obtained results, it is found that average power saving is more for half adder and half subtractor implemented using PFAL technique when compared to other techniques of partial adiabatic logic including conventional CMOS logic.