FPGA Design and Implementation of DVB-S2/S2X LDPC Encoder

A new FPGA architecture of the DVB-S2/S2X LDPC FEC encoder with low number of resources consumption is proposed. The encoder is full rate compatible and supports all code rates from DVB-S2/S2X standards. In addition, all frame types (normal, medium and short) are supported. The proposed architecture is based on iterative addresses calculation of parity bits accumulators and actively reuses parity calculators and parity storage. The Kintex FPGA implementation of the proposed architecture is done resulting in less than 3000 look-up-tables and flip-flops and only 6 block memories usage.