A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System

FPGAs can be a promising accelerator used for MEC (Multi-access Edge Computing) which provides timing critical services for a number of terminals at the base stations near from edges. Although a high-end FPGA can support a fixed latency computation with a relatively small power consumption, they are expensive and the available acceleration circuits are limited into a size of single FPGA. FiC (Flow-in-Cloud) has been developed for building a virtual large FPGA from a number of middle-range economical FPGAs connected with high speed serial links. Although the current target of FiC is cloud computing, it is more suitable for the future MEC, because huge hardware resource can be supported with small cost. One of the problem to use such multi-FPGA systems for timing critical computation is network uncertainty. With a common packet switching, the computation speed is influenced with the network traffic. That is, the fixed latency computation which could be supported by a single FPGA is hard to be supported with multi-FPGA systems using common packet switching networks. In order to address this problem, we introduced STDM (Static Time Division Multiplexing) switch in the FiC system. Since the STDM always supports a constant communication latency, transfer time can be estimated beforehand. Through the implementation of the STDM switch on the FPGA board for FiC, it appeared that the utilization ratio of the LUTs for the STDM switch is smaller than 14%. The required number of slots is less than 16 even for a system with 256 nodes. We implemented the Conjugate Gradient method, which includes all-to-all communication, on 4x2 FiC system. It achieved 17.9 times performance improvement of Intel E5-2667 2.90GHz CPU with 6 cores.