An Upper Bounder Evaluation Method of Error Probability for SRAM FPGA

Because of the high integration, low cost and high performance, SRAM FPGAs are becoming increasingly attractive in space missions. However SRAM FPGAs are vulnerable to SEU , so SEU protective measures must be taken and the fault-tolerant capability of FPGA application should be evaluated before it was deployed on obit. In this paper, the relationship between the number of SEU and error probability of SRAM FPGAs was studied by a model, and this relationship was validated by both fault injection and heavy ion irradiation experiment. Then on the base of it, a quick method to evaluate the upper bounder of the error probability for the FPGA application was proposed, and by this method, the error probability of the FPGA’s application can be achieve by fewer fault injection campaigns.