Sizing techniques for delay optimisation of 4-bit dynamic CMOS Manchester carry chain

One of the most popular circuit topologies in VLSI systems is dynamic CMOS. The performance of such a circuit depends predominantly on its transistor sizes. In this paper, the problem of optimal sizing of the transistors in one of the popular dynamic CMOS circuits. i.e. Manchester Carry Chain is examined and sizing technique for the same are analyzed for delay optimisation. Manchester Carry Chain comprises of pass transistors and CMOS inverters in a domino logic implementation. Delay was noticeably improved by 19% utilizing the linear delay model along with Hi-Skewed inverter technique, dynamic logic sizing and El-more delay model. Simulations were done using cadence virtuoso's gpdk180 library. Post layout simulation was also performed to analyze the effects of parasitics on delay and power.