Comparative Research for Managing Delay in Signal Processing via Multipliers

In the present era, need of compact devices with low power consumption & portably has created the need of Integrated circuits and when these devices are used for signal processing, multipliers plays a vital role & has become dominant functional blocks in processors and microcontrollers. Thus it has become crucial to explore a algorithm for fast multiplier that enhance structural design to increase speed & minimize area. This paper introduces the Array, Vedic, Wallace & Dadda Algorithms & a performance comparison between them. In this manuscript simulation has been done for the mentioned algorithms for different bit lengths i.e. two, four, eight & sixteen bit on Model-Sim using VHDL language and then their implementation them on Xilinx for comparative analysis.