A Low Output Voltage Ripple Fully-Integrated Switched-Capacitor DC-DC Converter

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 3.3 V to 1.5 V with a peak efficiency of 68% is implemented in a 2P3M 0.6-μm CMOS process with a 555 pF poly-poly flying capacitor and a 1.34 nF MOS tank capacitor. This paper demonstrates a means of applying a low-frequency input clock as part of a time-interleaving technique for a symmetric charge-discharge topology that reduces the output voltage ripple. Burst-mode pulse-frequency modulation is used to maintain high efficiency over a wide range of load currents. A maximum 27 mV in output voltage ripple is measured for load current between 590 μA and 8 mA. In response to a load transient from 560 μA to 5.1 mA, the SC converter shows no undershoot and an overshoot of only 19 mV. Measured load regulation is 13.2 mV/mA.