Design of Double Gate Nano-FET

A Double Gate (DG) Nano-FET is developed here with the concept of heterostructure on insulator (HOI) and strain engineering infused in the channel region. The device developed provided better control over the leakage current on introduction of the second gate in bottom side of substrate leading to nominal carrier mobility due to the strained SiGe layer sandwiched between two layers of Strained Silicon (s-Si) for both the gates. The DG nano structure is developed on 45 nm technology and provided ~63% enrichment in leakage in comparison to the 40 nm tri-layered HOI MOSFET, but lattice mismatch scattering degraded the devices performance. Thus, with a predominantly smooth characteristic curve less leakage current is observed for the DG Nano-FET device.