Single-Pulse Avalanche Failure Investigations of Si-SJ-mosfet and SiC-mosfet by Step-Control Infrared Thermography Method

The step-control infrared thermography method was proposed to investigate comprehensive single-pulse avalanche failure details of Si-superjunction (SJ) mosfet and SiC-mosfet. By this method, the damage location and even its shift in real time during the whole avalanche process can be observed. It is shown that, for the Si-SJ-mosfet, the avalanche damage location is extended from the cell region toward termination region with the increased avalanche time. The parasitic bipolar junction transistors at the cell corner near the termination are triggered due to the increased p-base resistances under relatively high temperature. However, for SiC-mosfet, the avalanche location is always kept within the cell region mainly due to insensitive breakdown voltage dependence on temperature. As a result, its failure site is found to locate at the source pad near the wire bond, likely due to the lattice temperature beyond the melting limit of aluminum contacts. Finally, the schemes to improve avalanche robustness, including the two different N-Epitaxy layers for Si-SJ-mosfet and the double source wire bonds for SiC-mosfet, have been proposed and verified basing on different failure mechanisms.