Ultrafast Characterization of Hole Trapping Near Black Phosphorus–SiO2 Interface During NBTI Stress in 2-D BP p-FETs

2-D p-channel FETs with black phosphorus (BP) channel and silicon dioxide (SiO
₂
) gate oxide have been fabricated. An ultrafast characterization method (10-μs delay) is used to measure the shift in threshold voltage (V
_T
) during and after negative bias temperature instability (NBTI) stress under different gate biases (VGSTR) and temperatures (T). The V
_T
stress and recovery kinetics are ascribed to hole trapping and detrapping (V
_HT
) near the BP-SiO
₂
interface, due to the choice of channel material, SiO
₂
thickness (T
_OX
), and stress (V
_GSTR
/T) conditions. A detailed analysis is done to determine the projected magnitude of V
_T
without any delay, for different VGSTR and T, and at thinner T
_OX
relevant for realistic end-use cases.