Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes

Polar code has gained worldwide recognition due to its capacity-achieving property. The fast simplified successive cancellation flip (Fast-SSC-Flip) algorithm improves the frame error rate (FER) performance of successive cancellation (SC) decoders with extra metric computations. However, the metric includes exponential operations, which is inefficient to implement. In this work, one shift operation and one addition are employed to approximate the exponential operations with negligible performance loss. Besides, the metric computations of more constituent codes (Type-I to Type-V) are derived that the complexity of Fast-SSC-Flip is further reduced. Simulation results show that the FER performance of the improved Fast-SSC-Flip algorithm with list size λ = 8 outperforms that of the Fast-SSC algorithm by 0.7dB. Moreover, based on the proposed algorithm, an efficient hardware architecture is first developed. It uses less look up tables and achieves a maximum throughput of 140.6 Mbps at high SNR on the Altera Stratix IV EP4SGX530KH40C2 FPGA. Compared with the state of art Fast-SSC implementation, the proposed architecture has a higher resource utilization efficiency (throughput per look-up tables). Under the 28 nm CMOS technology, the throughput can reach up to 483.8 Mbps at a clock frequency of 704 MHz.