Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic

This paper presents the post-layout simulation of our proposed Current Pass Optimized (CPO) adiabatic logic for cryptographic circuit. By using dummy transistors in the input function, CPO-adiabatic logic circuit consumes uniform current irrespective of the input data being processed; therefore CPO-adiabatic logic is more resistant to differential power analysis attacks than the conventional secure adiabatic logic families. To evaluate the circuit performance, we compare the post-layout simulation results of CPO-SPGAL and CPO-EE-SPFAL GF(2^4) multiplier. From the simulation results we illustrate that the CPO-EE-SPFAL is a secure logic compared with CPO-SPGAL.