Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs

In this paper, we propose simple but effective clock tree optimization algorithms for monolithic 3D ICs that are based on tier partitioning and flip-flop relocation. Our algorithms take into account 3D timing critical paths, clock skew, and the clock tree hierarchy for a better quality 3D clock tree. We also perform clock slew manipulation and buffer reduction to further improve the 3D designs. We tested four industrial benchmarks implemented using a commercial library and observed up to 34.3% clock skew, 35.9% clock wirelength, 10.0% combinational clock power, and 15.5% total power savings compared to the state-of-the-art [8].