Thermal and Mechanical Simulations for Fan-Out Wafer-Level Packaging Technology: Introduction of a "Solder Heatsink"

The present study focuses on a 3D module composed of two stacks of 8 silicon chiplets interconnected with copper Through Molding Vias and ReDistribution Layer realized in Fan-Out Wafer-Level Packaging technology. The thermal management of such 3D module has been identified as a critical issue. The proposed multi-strata and multi-chiplet package is studied by means of numerical simulations with a focus on its thermal and thermo-mechanical behavior. After a description of the FO-WLP technology, a first part is dedicated to thermal simulations. After identifying the thermal impact of several parameters, we propose two thermal improvements: 1/ the addition of a thin graphite heatspreader on top of the 3D module. 2/ Solder a large area of the 3D module on a highly thermally conductive substrate in order to improve the bottom heat removal, as it is done in power module packaging. The second part is dedicated to the thermo-mechanical study of the 3D module and more precisely to the comparison between a ball grid array and the proposed thermal solution with the "central solder heatsink".