RDL-1st Fan-Out Panel Level Packaging (FOPLP) for Heterogeneous and Economical Packaging

Established RDL-1
^st
fan out panel level packaging (FOPLP) processes and modules for Gen 3 panel (550x650 mm) sizes. RDL-1
^st
package test vehicle (TV) has been designed and fabricated with single chip size of 10x10mm and final package size is 15x15mm. IC test chip has been designed and fabricated with Al pad structures and copper pillars with solders for final package assembly. Extensive mechanical modelling and simulation studies have been conducted to provide optimum guide lines for process design and material selection. Multilayer RDL structures up to two layers have been fabricated with copper RDL line width and line spacing (LW/LS) of 8/8um. Number I/Os for this package is around 1000. Prior to final TV fabrication several short loop DOE evaluations have been conducted for material and process feasibility. A special mask set with test structures has been designed for short loop DOE and it includes LW/LS structures and meander structures from 1/1um to 15/15um, via opening structures from 3um to 20um. Established lithography process to resolve LW/LS patterns from 2/2um onwards. Several key modules for panel processing like seed layer deposition, plating, wet etching and final assembly, have been established by closely working with equipment and material suppliers.