Development of a no Reflow Cu Pillar Bump to Improve Chip/Package Interactions (CPI) Process and Reliability Performance

The no reflowed copper (Cu) pillar bump behavior during front-end process and performance of flat solder capped Cu pillar assembled with bump on trace (BOT) processed by mass reflow is measured and analyzed. The interconnections with two different solder cap structures were tested: Cu post capped with flat lead-free solder tip (without front-end reflow) and Cu post capped with round lead-free solder tip (with front-end reflow). Emphasis is placed on the risk of high solder tip height on small bump size in front-end process and assembly performance of the different solder capped Cu pillar bump structures. The package size of test vehicle (TV) is 116 mm
²
with a daisy-chain die size of 7 × 8 mm
²
. The minimum pitch is 100μm with critical mixed bump size design in a die. The bump stack-up with 4 different solder tip ratios (reflowed solder tip height divided by minimum UBM size); 0.45, 0.56, 0.67, 0.78 are investigated and the CPI performance based on bump stack-up with different solder tip ratios are collected and analyzed. All the different solder tip structures formed before and post front-end reflow have been evaluated and compared by employing package level reliability test following JEDEC include thermal cycling test, high temperature storage test and unbiased highly accelerated Test.