Retargeting the MIPS-II CPU Core to the RISC-V Architecture

This paper presents the process of retargeting the existing single-issue, six stage pipeline processor core based on MIPS-II architecture to the RISC-V architecture. Both ISAs were compared and necessary code changes were implemented to the original Verilog HDL code. After retargeting, the entire processor was preliminary verified with functional simulation using RISCV-tests and RISCV-compliance suites. Moreover, performance comparison between two ISAs was carried out using the Dhrystone and CoreMark benchmarks.