Design of a Low-Power Linear SAR-Based All-Digital Delay-Locked Loop

A 500 MHz to 1.5 GHz 8-bit SAR-based all-digital delay-locked loop (ADDLL) designed and simulated in a 130 nm CMOS technology is presented in this paper. The proposed ADDLL employs a novel digitally controlled delay line (DCDL), which presents a good linearity for the SAR code-delay curve and low power consumption. Compared to other SAR-based ADDLLs, there is no complex binary to thermometer decoder in the proposed DCDL that leads to low power dissipation and small area. Based on the simulation results, the proposed DCDL is fully monotonic and exhibits a good performance in terms of linearity at all PVT corners. The presented ADDLL locks in 32 cycles of input clock and dissipates 1.15 mW at 1.5 GHz clock frequency and 1.2 V supply voltage.