Silicon MOSFETs (conventional and non-traditional) at the scaling limit

Summary form only given. Scaling planar MOSFET devices has been the dominant technology option for the past three decades and it is likely that this trend will continue for another decade. Beyond that point, significant materials and device issues arise, which may open the door for alternative device structures. The "showstoppers" a decade hence include gate insulator scaling, shallow junction technology, short channel effects and off-state leakage current in devices with scaled threshold and power supply voltages. It has been shown in recent years (Frank et al, 1992; Auth and Plummer, 1997) that double-gated or vertical surround gate MOSFET structures can extend MOSFET scalability perhaps to channel lengths on the order of 20 nm. This is primarily because these new gate geometries provide tighter control of channel potentials than is the case in conventional planar MOSFETs. These alternative geometries do not however eliminate the gate oxide and parasitic resistance issues of extended scaling. In some respects they complicate these issues because, for example, gate dielectrics must now be grown on nonplanar surfaces. Perhaps more interesting than extended scaling, the vertical MOSFET configuration provides new device design options and opportunities for higher levels of functional integration. Since the channel is vertical, arbitrary doping profiles, heterojunctions and multiple devices can be grown epitaxially into the channel structure. Alternatively, once the pillars are formed, ion implantation can be used to create stacked N and P regions that implement complex functions.