A Review on the Effects of Technology on CMOS and CPL Logic Style on Performance, Speed and Power Dissipation

With the advancement in CMOS technology, process related limitations, power dissipation, leakage etc. are main challenges for VLSI. So, in the field of VLSI an alternative device technology is the need of the time. Many new next generation devices have come up very recently, especially, the Carbon Nanotubes (CN)Field Effect Transistor (CNTFET)which has many advantages over conventional MOSFETs. MOSFETs like CNTFETs are the best for high-performance VLSI design as it fits well with the traditional MOS-VLSI design. This work presents an inclusive study and analysis of the results of simulation on different logic families. Moreover, the effect of technology nodes on leakage, power and delay are also highlighted in this simulation study. The logic families considered here are the conventional Complementary-Metal-Oxide-Semiconductor (CMOS)and Complementary-Pass-transistor-Logic (CPL)logics along with the CNTFET based logic. Based on these logic styles, NAND, NOR, XOR and multiplexer are implemented. An analysis is carried out to calculate power, worst delay and power delay product (PDP). This work will give the best select of logic style for VLSI applications useful for low power and high speed. The simulation is done by using Synopsys HSPICE tool with 90nm and 32 nm CMOS technologies and whereas for CNTFET 32 nm CNTFET model is chosen. The results show that the performances of the CNTFET based logics are superior compared to other logic families at different CMOS technology nodes.