Minimizing Ripples of Inductor Currents in Coupled SIDO Boost Converter by Shift of Gate Pulses

Single-input dual-output (SIDO) dc–dc converters have gained attention with the increasing need of multiple voltage levels. Magnetically coupled inductor SIDO (CI-SIDO) boost converter is the topology focused in this article. Ripples in inductor currents play important role in design of dc–dc converters and need to be as low as possible. The shift of one gate pulse with respect to another gate pulse has been used in converters, such as interleaved boost for reducing ripples. However, unlike interleaved boost, CI-SIDO boost has unequal output voltages and unequal inductances. The values of shifts, at which ripples are minimized, vary under different conditions of CI-SIDO boost. So, the analysis to reduce ripple in interleaved boost is not applicable for CI-SIDO boost. This article presents a detailed analysis of CI-SIDO boost converter for obtaining minimum ripples by shifting gate pulses. The analysis accounts for all permissible combinations of output voltages and inductances. Ranges of shifts in gate pulse are found, for all conditions, to achieve minimum ripple in each inductor current separately, and both inductor currents simultaneously. The practical applications of the analysis are shown by giving examples. The ranges found are verified by simulation in MATLAB/Simulink and experiments on laboratory prototype.