Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET

In this paper, the overall performance of a stacked nanoplate FET was analyzed as a candidate for a 3.5-nm node. In order to conduct this analysis, Monte Carlo (MC) simulation was used to obtain near-realistic data and 3-D TCAD simulation data were fitted under the consideration of strain engineering. Through this process, the characteristics of the stacked nanoplate FET were analyzed in terms of structure optimization. In addition, strain effect, as one of the mechanical effects, to enhance the performance for nanoplate FET was simulated with the fitted data. This enhancement is predicted to deteriorate the performance by self-heating effects (SHEs). Therefore, the way in which ON-current (
${I}_{ \mathrm{\scriptscriptstyle ON}}$
) increased by strain engineering influences SHEs was investigated, and appropriate strain engineering to obtain the best performance was proposed. Finally, the above analysis was confirmed using the Berkeley Short-channel IGFET Model Common Multi-Gate model.