A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a
$0.17~ {\mu }\text{m}$
SOI layer with a source field plate covering the full drift region. Low specific on-resistance
${R} _{\text {on,sp}}$
is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage
${V} _{\text {B}}$
of 960 V with a superior figure of merit (FOM
$= {V} _{\text {B}}{^{\text {2}}} / {R} _{\text {on,sp}}$
) of 5.98 MW/cm
₂
when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.