Double Strained Channel MOSFET: Deep Into Sub-Microns

Development of MOSFET with an intrusion of two strained silicon layers in the channel region has been carried out leading to the advent of 50nm and 100nm channel length devices. Further scalability and device sustainability analysis for reduced gate length of sub-50nm regime have been due, which has been now the focus of this paper. The 50nm technology node device has been scaled down to 30nm channel length and the device characteristics have been examined leading to ~88% enhancement in drive curren.