On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time

MISR compaction technique has multiple advantages like single cycle signature comparison, effective use of scan I/Os compared to XOR-based compaction. Main disadvantages with this technique are poor diagnostic capabilities due to loss of data correlation during compaction and complete signature corruption due to X-sources. In this paper, we present a new MISR architecture and methodology to improve the diagnostic resolution of MISR signatures by comparing the intermediate MISR signatures after regular intervals of time. We also propose an enhancement to this architecture with reset logic to improve the diagnosis further, improve the immunity against X-sources and also detect the faults early, thus reducing the tester time and test cost. These logic changes were implemented on ISCAS benchmarking designs and results have been tabulated.