A Design Method of Phase-Locked Loop for Grid-Connected Converters Considering the Influence of Current Loops in Weak Grid

Phase-locked loop (PLL) with improper bandwidth could lead to potential instability issues for the grid-connected voltage-source converters (VSCs) under weak grid conditions. The current loops of the VSCs can be designed faster as the development of the silicon carbide (SiC) and gallium nitride (GaN) semiconductor materials. It is questionable whether the PLL's bandwidth could also be designed higher for faster current loop. Hence, the relationship between the bandwidth of the current loop and the bandwidth of the PLL is studied first. It is revealed that the bandwidth of the PLL might not be increased linearly with the increasing of the bandwidth of the current loop, and thus, the traditional design principle, i.e., the bandwidth of the PLL is not higher than one-tenth of that of the current loop, might no longer be suitable. Thus, this paper proposes a design method of the PLL to make the grid-connected VSCs to have adequate stability margin and satisfactory dynamic performances under weak grid conditions. The current loop is designed independently, while the PLL is designed considering the coupling between the current loop and the PLL under weak grid conditions. The simulations and experimental results verify the theoretical analysis and the proposed design method.