Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration

VLSI design teams have vast amounts of legacy RTL code that has been manually optimized to execute a particular task within a given performance, area, and power budget. The main problem is that these fixed architectures cannot be easily re-used in future projects which require different performance, area and power constraints mixes. Thus, in this work we introduce a method to abstract RTL descriptions into synthesizable behavioral descriptions which in turn allow the generation of a new micro-architecture with the newly desired characteristics. In particular, this work, presents a set of optimizations that allow to generate a larger number of micro-architectures compared to the state-of-the-art RTL to C compilers based on two main optimizations: Array merging and loop fusing. Experimental results show that our optimization method is efficient in extending the variety of micro-architectures found and hence increasing the re-usability of these designs.