Modeling of HCD Kinetics for Full ${V}_{{G}}$ / ${V}_{{D}}$ Span in the Presence of NBTI, Electron Trapping, and Self Heating in RMG SiGe p-FinFETs

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift (ΔV
_T
) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain (V
_D
) and gate (V
_G
) voltage space and calculates the generation of interface traps for pure HCD (ΔV
_IT-HC
) and for negative bias temperature instability (NBTI) (ΔV
_IT-BT
), hole trapping (ΔV
_HT
), and electron trapping (Δ
_VET
) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10-μs delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying V
_G
and V
_D
stress in the presence of SHE but no HCD.