Performance Analysis of Classical Two Stage Opamp Using CMOS and CNFET at 32nm Technology

This paper presents performance analysis for the two-stage CMOS operational transconductance amplifier using conventional CMOS technology and emerging carbon nanotube technology. Both the theoretical calculations and computer aided simulation analysis have been given in detail. Designs have been carried out on backend tool of Mentor graphics using PTM 32nm CMOS process. Schematic simulations have been carried out using `Pyxis Schematic' and simulations have been done using simulator `ELDO', version 11.2. For CNFET implementation 32nm CNFET model from Stanford University is used and simulations are carried out using Hspice. The a. c. analysis demonstrates that gain of the CMOS amplifier is very low i.e. 15.6 dB, Phase Margin is 80.2°, & Unity Gain Bandwidth is 7 MHz. The output swings up to 1.15V and the op-amp dissipates power of 336.5μW under supply voltage of 1.2V. The comparative performance analysis with CNFET shows that there is improvement of 264 percent in gain while maintaining the complete stable performance in both the case. Further results show the tremendous increase in unity gain bandwidth while significantly saving in power.