High-Speed Pattern Matching Architecture on Limited Connectivity FPGA

State-of-the-art Field Programmable Gate Arrays (FPGA) are characterized by high frequency of operation, big volume and high bandwidth of its internal memory, which makes them very promising for rapid pattern matching systems realization. Large-scale data structures with high-level of internal connectivity of its elements require parallel data processing architectures with correspondent level of internal connectivity of its blocks. In this paper, we discuss different fields of application of the suggested by the authors approach to map one-dimensional input pattern to the two-dimensional FPGA processing structure with limited connectivity of its elements. Experimental and theoretical research have shown that synthesized on FPGA multicluster architectures for patterns with finely granulated structure matching are characterized by more than 90% utilization of FPGA memory bandwidth, low time delay of 3-5 clock cycles. For input patterns with coarse structure, effectiveness of FPGA memory elements use can decrease to 80%, data processing time delay increases to 5-6 clock cycles.