Pattern Translation Tool for Post-Silicon ASIC Testing

Post-Silicon design validation of digital ASICs on Automated-Test-Equipment (ATE) require test vectors for chip functional verification. These test vectors are generated by running post-layout design simulations. Integrated Circuit (IC) Design tools let these simulation waveforms dumped in industry popular formats like Value Change Dump (VCD)/ Extended Value Change Dump (EVCD) and Standard Test Interface Language (STIL). Once a chip gets fabricated these pattern files are used by IC test engineer to test the chip for intended functionality using VLSI testers. Not all these test pattern file formats are directly portable on all testers. Some VLSI testers need test vectors in STIL and others only accept tester specific compressed pattern formats. Only few test pattern conversion utilities are available commercially in the market. Making test pattern conversion process easy can save test engineers efforts and faster design-to-test cycle. This paper describes development of one such pattern conversion software to make test pattern conversion process fast and efficient. We have named this tool as PATCON; an acronym for Pattern Conversion.