A Design Space Exploration Method for On-Chip Memory System Based on Task Scheduling

As technology scales in the past sixty years, System on-Chip (SoC) has become the inevitable direction of chip development. Multi-core processor as one of the SoCs is the most effective solution to balance the performance and power. However, the bandwidth of chip system has become the bottleneck for multi-core processor. Improving the bandwidth of off-chip memory system or introducing a well-designed on-chip memory system can solve this issue relatively. In this paper, we introduce a design space exploration method based on task scheduling to guide the design of on-chip memory system. Using this method, the utilization of cores can reach a high level under the benchmark of DGEMM and some hardware constraints. In addition, we conclude some relationships for the parameters of the multi-core architecture, which can instruct us how to design appropriate on-chip memory system.