High frequency simulation of through-silicon via(TSV) failure

3-D integration technologies have been of increasing interest for compact and high-performance system integration and packaging. Through-silicon-via (TSV) is one of the key technologies to enable vertical connections for stacked ICs and silicon packages. However, some TSV structural defects such as pinholes and voids are difficult to capture as they commonly affect TSV performance parameters rather than TSV logical function. In this paper, the high frequency characteristics of tapped-TSV channels with defects are analyzed by inserting various amounts of the void defect.