TCAD Simulation Study of 90 nm Junctionless SOI MOSFET

The results of TCAD study of electrical characteristics dependences of 90 nm junctionless single-gate SOI MOSFET structural and technological parameters are presented in the paper. Electrical characteristics have been simulated using the Sentaurus TCAD tool. It is shown that the leakage current of the 90nm transistor increases substantially with drain-source voltage V
_ds
<; 1.2 V due to the avalanche generation of carriers near the drain-gate boundary. A decrease in the substrate thickness from 70 nm to 40 nm makes it possible to weaken the avalanche generation and achieve a low level of the leakage current up to I
_off
≈ 1 nA /μm.