Design of a Low-Power 12-bit SAR ADC

In this paper a 12-bit successive approximation analog-to-digital converter (ADC) is presented. The circuit is realized in a standard 1.8 V 180 nm CMOS technology. To avoid using of an operational amplifier, a passive sample-and-hold circuit is applied. A capacitor-based digital-to-analog converter allows for power saving. The ADC has conversion rate of 1 MSps and the signal-to-noise-and-distortion ratio of 52.1 dB with power consumption of 53 microwatt. Digital calibration and correction help to further improve the ADC characteristics.