Boundary Scan Extension for Testing Distributed Reconfigurable Hardware Systems

This paper deals with testing a distributed reconfigurable hardware systems (DRHSs) by proposing a new extension of the IEEE Std. 1149.1 named reconfigurable joint test action group (RJTAG). The first step introduces an extension of the boundary scan architecture by changing the usual boundary scan register (BSR) into a reconfigurable BSR. The second extends the JTAG key instructions that cover reconfigurable internal test and reconfigurable external test. For a coherent testing of different subsystems, a global DRHS test algorithm is proposed. The basic idea behind coherent testing is to enable testing of dependent circuits and their interconnections according to the coordination and interconnection matrices. Finally, in order to illustrate the effectiveness of the proposed algorithm, we have conducted experiments on combinational and asynchronous sequential DRHS.