Effects of ZrO2/Al2O3 Gate-Stack on the Performance of Planar-Type InGaAs TFET

We investigate the impact of gate-stack engineering using W/ZrO
₂
/Al
₂
O
₃
on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO
₂
with the dielectric constant of around 40 on In
_0.53
Ga
_0.47
As. On the other hand, the reduction of Dit by insertion of ALD 1-5 cycle Al
₂
O
₃
interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO
₂
/Al
₂
O
₃
IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S.Smin) of 55 mV/dec and ION of 0.88 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, and IOFF = 10 pA/μm). Furthermore, the ZrO2/Al2O3 IL gatestack is applied to the optimized In
_0.75
Ga
_0.25
As quantum well (QW) channel TFETs. The low S.Smin of 50 mV/dec and high ION of 1.2 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, IOFF = 10 pA/μm, and CET = 1.1 nm) are demonstrated by combing the present ZrO
₂
-based gate-stack with the optimum In
_0.75
Ga
_0.25
As QW channel structure.