Optimization Method to Eliminate Turn-on Overvoltage Issue of the High Voltage SiC Super-Cascode Power Switch

A potential overvoltage issue during turn-on transient of the silicon carbide (SiC) junction gate field-effect transistor (JFET) based high voltage super-cascode power switch (SCPS) is first identified. The overvoltage issue caused by the JFET slow sequential turn-on is investigated, and the corresponding mitigation method is proposed. Based on this, an optimization method is proposed to improve JFET voltage balancing during off-state as well as eliminating the overvoltage during turn-on transient in the high voltage SiC super-cascode structure. The analysis is verified with experimental results. The overvoltage on the top JFET is eliminated and the total turn-on time is reduced from 518 ns to 82 ns. In the end, the influence of the voltage balancing capacitor tolerance on the voltage distribution is discussed.