A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS

This paper presents a programmable wideband equalizer with hybrid Continuous-Time (CT)/Discrete-Time (DT) architecture. Unlike the conventional hybrid CT/DT LPF, the proposed circuit enables large compensation level (CL) at high peaking frequencies. A prototype has been fabricated in 28 nm CMOS. The proposed equalizer achieves up to 7 GHz peaking frequency with more than 10dB of CL. In addition, it offers capacitance ratio ( C ratio) and clock frequency (fCK) programmability. The proposed equalizer occupies 0.061 mm
²
of active area.