Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

This brief presents the design of an energy efficient flash analogue-to-digital converter (ADC) with threshold inverter quantiser comparator employing advanced body biasing to compensate for the effects of parameter variability. The proposed calibration scheme is verified against process, voltage, and temperature corners as well as random parameter variability (mismatch). Two proof-of-concept ADCs of 4- and 6-bit precision are designed and verified in simulations in 28 nm fully depleted silicon on insulator technology. The 6-bit converter achieves sampling rate of 3 GS/s, energy efficiency per conversion step below 20 fJ, and precision of 5.2 effective number of bits. The proposed ADC architecture is dedicated to high-speed and low-precision applications, such as communication transceivers and data acquisition systems where area and energy efficiency are paramount.