Comparative Analyses of Low-Power IC Design Techniques based on Chip Measurements

Vast number of analyses of the mainstream lowpower techniques like power gating, clock gating, Dynamic Frequency and Voltage Scaling (DVFS) and Adaptive Voltage Scaling (AVS) are presented. Direct on-chip measurements were performed on a small test chip produced in IHP 130nm technology which are to be used for building the power strategy of a complex multiprocessor chip. Results showed that for a marginal performance loss, power reduction of 3,5x is possible by downscaling voltage and frequency, while downscaling only voltage leads to power reduction of up to 65%. They further showed that voltage regulators may actually lead to increased power consumption in some cases if care is not taken. In the same time, the paper presents a design strategy for the power architectures of complex Systems-on-Chip.