A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS

This paper presents a noise-shaping SAR ADC for IoT sensor applications. The ADC exploits a 2
^nd
-order passive noise-shaping loop without a quiescent current. To reduce harmonic distortion induced by mismatches between MSBs, thermometer-coded 3-bit MSBs are implemented with a simple shift register-based dynamic element matching (DEM) technique. Furthermore, a programmable majority-voting (PMV) technique for LSB decision is applied in order to relax noise requirement of a comparator. With the DEM and PMV, SFDR, SNDR and SNR are enhanced by 9.8, 4.7 and 1.9 dB at a 1.0 V supply, respectively. For 50 kHz BW, the modulator dissipates 74.5 μW from a 1.0 V supply and achieves a peak SNDR of 72 dB, a peak SNR of 72.2 dB and a DR of 73.8 dB. The prototype modulator is fabricated in 28 nm CMOS technology, occupying an area of 0.0575 mm
²
.