Higher radix Kogge-Stone parallel prefix adder architectures

In this paper, we describe the design of radix-3 and radix-4 parallel prefix adders, that theoretically have logical depths of log/sub 3/n and log/sub 4/n respectively, where n is the bit-width of the input signals. The main building blocks of the higher radix parallel prefix adders are identified and higher radix structures of Kogge-Stone Adders are presented. We show that with the higher radix architectures the logic depth can be reduced by 50% and the cell count can be reduced as much as 47% for 64-bit adders. Simulation results indicate that radix-4 adders can be more than 30% faster than radix-2 realizations.