FPGA Implementation of PS-PWM for Single-Phase Thirteen-Level Cascaded H-Bridge Multilevel Inverters

An FPGA implementation of PS-PWM for a single-phase thirteen-level CHB-MLI is proposed in this paper. For this reason, a detailed investigation of implementation of PS-PWM in FPGA through VHDL modules is held by examining each module and algorithms of them separately. Finally, gating signals are observed in simulation environment and verification of them is done by the experimental studies.