A Self-Timed Ring Based Time-to-Digital Converter on FPGA

Time-to-digital converters (TDCs) are critical for systems that need accurate time measurements. This paper presents a self-timed ring (STR) based TDC on FPGA. The TDC is implemented on Xilinx Virtex XC5VLX50T FPGA. Through manual placement and routing, a 61-stage STR based TDC is implemented which can achieve 22.2ps resolution consuming 585 LUTs and 265 registers.