Research on Design and Test Method of High Performance 6 Input LUT

FPGA devices are becoming more widely used in various industries due to their field-programmable features. Its basic unit in configurable logic block(CLB) is the look-up table(LUT), which takes the important part in whole path delay. Most of the previous LUTs are based on the structure of NMOS transmission tubes or CMOS transmission gates. These structures have the defects of large area, large power consumption and poor performance. In this paper, a LUT structure of decoding transmission gate is designed, which has better area power delay product(APD) performance. At the same time, multi-threshold voltage design is adopted to reduce the leakage current of the circuit under the premise of ensuring the function. All of its APD is 47.4% better than the structure we compared. Finally, an area-saving ring vibration test circuit is designed, which is used to test both the rise and fall propagation delay of each inputs to the output and has 158% area saving than the simple test chain.